1. Field of the Invention
The invention relates generally to horizontal readout registers of charge coupled device image sensors and specifically to structures that provide efficient distribution of high speed clock signals to such readout registers.
2. Description of Related Art
Charge couple devices (hereinafter CCDs) are widely used in video imaging and recording applications. An application of a CCD sensor is industrial inspection or vision equipment. The architecture of a CCD video sensor for this application may be optimized for maximum pixel resolution, or to maximize image frame rate, or both. Often inspection cameras used to inspect moving objects (e.g., on a continuous conveyor belt or rolled goods such as rolls of cloth) employ a line scan CCD sensor where a linear CCD sensor is oriented in a direction perpendicular to the direction of movement of the object being imaged. Advanced linear CCD sensor often employ an time delay and integrate technology and are referred to as TDI CCD sensors.
In FIG. 9, known TDI CCD sensor 100 includes imaging section 102 coupled through transfer gate 104 to horizontal CCD readout structure 106. Imaging section 102 includes a plurality of column registers (also called vertical CCD registers, VCCDs), each column including a plurality of photo-sites. In operation, a camera lens focuses an image conjugate on the TDI CCD sensor. The actual object, that forms image conjugate that is the optical input to the TDI CCD sensor, is moving (e.g., on a conveyor belt). Thus, an image conjugate focused on the sensor appears to be moving across the sensor. A portion of the image first appears on one pixel of the TDI CCD sensor, and then appear on another pixel of the sensor. The camera and sensor are arranged so that a portion of the moving image moves in a direction from the top of a column of photo-sites to the bottom of the column. The TDI CCD sensor is clocked to transfer charge down the columns of photo-sites at a rate equal to the rate that the portion of the image moves down the column. Charge generated at a first photo-site is transferred to the next photo-site at the same time that the image portion that generated the charge at the first photo-site moves to the next photo-site. In this way photo-charge is accumulated at the photo-site under the image portion as the image portion moves down the column. Thus the name, time delay and integrate (TDI).
In a TDI CCD sensor, the last pixel in each integrating column of photo-sites (i.e., the last horizontal line) is transferred into a horizontal CCD readout shift register (HCCD) through a plurality of transfer gates controlled by a transfer clock signal TCK, each transfer gate corresponding to a column of photo-sites. Signal TCK is usually generated by circuits external to the CCD sensor, provided at interface pad 108 of the CCD sensor and from there distributed through a bus to the gate electrode of each transfer gate.
Adjacent to the image region is a horizontal CCD shift register (HCCD shift register) 106 which transports the signal charge from the imaging pixels to the output buffer 110. It is not uncommon for this HCCD to require 3-5 control signals. A typical 4-phase HCCD requires five control signals: four to control charge transport along the HCCD (e.g., clock signals A, B, C, D) and one to control charge transfer (e.g., TCK) from the image pixels to the HCCD. These control signals must span the entire length of the image region.
Clock signals A through D are usually generated by circuits external to the CCD sensor, provided at interface pads 112, 114, 116 and 118, respectively, of the CCD sensor and from there distributed through busses to the gate electrodes that control the shifting of the HCCD shift register.
Those CCD sensors commonly referred to as linear sensors or TDI CCD sensors, typically have very long imaging regions. A typical high performance linear sensor has a 2.6 centimeter long image region consisting of 2,048 image pixels on a 13 micrometer pitch. This is not an extreme example; linear sensors longer than 6 centimeters are regularly fabricated.
An important limit to the maximum operating speed of a CCD is the propagation delay of the HCCD clocks along the length of the device. In a typical linear CCD, a clock signal, supplied from an external source to a bond pad on the die, is then distributed along a single metal bus spanning the length of the HCCD. The HCCD employs conductive poly-crystalline silicon (hereinafter poly-silicon) gate electrodes. These gate electrodes are connected to a metal bus along the length of the HCCD. Typically, the connection between the metal bus and the bond pad is made at only one end of the image sensor. For this case the propagation delay for the clock to reach the other end is given by N.sup.2 RC where N is the number of HCCD elements, R is the incremental metal bus resistance along one HCCD element and C is the capacitance of one HCCD element. For typical values of R=0.07 .OMEGA., C=100 fF, and N=1,024, the clock delay is 7.0 ns. The clock period should be at least four times the clock delay. Thus, this example has a maximum clock frequency of 35 MHz.
In addition to limiting maximum clock speed, the variation in clock delays along the CCD may degrade image quality by introducing a pixel-to-pixel non-uniformity. To prevent this degradation, it is desirable to have a clock delay much shorter than the clock transition time.
The present invention describes an alternative clock distribution structure that greatly reduces the clock delay to allow high speed operation without degradation in image quality.